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| FDM3300NZ February 2003 FDM3300NZ Monolithic Common Drain N-Channel 2.5V Specified PowerTrench MOSFET General Description This dual N-Channel MOSFET has been designed using Fairchild Semiconductor's advanced Power Trench process to optimize the RDS(ON) @ VGS = 2.5v on special MicroFET lead frame with all the drains on one side of the package. Features * 10 A, 20 V RDS(ON) = 23 m @ VGS = 4.5 V RDS(ON) = 28 m @ VGS = 2.5 V * > 2000v ESD Protection * Low Profile - 1mm maximum - in the new package MicroFET 3.3x3.3 mm Applications * Li-Ion Battery Pack D1 D1 D2 D2 D2 1 2 G2 8 7 6 5 3 4 S1 G1 S2 MicroFET Absolute Maximum Ratings VDSS VGSS ID PD TJ, TSTG TA=25oC unless otherwise noted Symbol Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Power Dissipation (Steady State) Parameter (Note 1a) (Note 1a) (Note 1b) Operating and Storage Junction Temperature Range 20 12 10 40 2.5 1.2 -55 to +150 Ratings Units V V A W C Thermal Characteristics RJA RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1b) (Note 1) 52 108 5 C/W Package Marking and Ordering Information Device Marking 3300N Device FDM3300NZ Reel Size 7'' Tape width 12mm Quantity 3000 units (c)2003 Fairchild Semiconductor Corporation FDM3300NZ Rev. E3 (W) FDM3300NZ Electrical Characteristics Symbol BVDSS TA = 25 unless otherwise noted C Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage, (Note 2) Test Conditions VGS = 0 V, ID = 250 A Min 20 Typ Max Units V Off Characteristics BVDSS TJ IDSS IGSS VGS(th) VGS(th) TJ RDS(on) ID(on) gFS Ciss Coss Crss RG ID = 250 A, Referenced to 25C VDS = 16 V, VGS = 12 V, VGS = 0 V VDS = 0 V 0.6 10.7 1 10 0.9 -3 16 20 22 10 35 1210 330 180 2.3 1.5 mV/C A A V mV/C m A S pF pF pF On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance On-State Drain Current Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance (Note 2) VDS = VGS, ID = 250 A ID = 250 A, Referenced to 25C VGS = 4.5 V, ID = 10A VGS = 2.5 V, ID = 9 A VGS = 4.5 V, ID = 10A, TJ=125C VGS = 2.5 V, VDS = 5 V VDS = 5 V, ID =10 A VDS = 10 V, f = 1.0 MHz V GS = 0 V, V GS = 0 V, 23 28 31 Dynamic Characteristics f = 1.0 MHz Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd IS VSD trr Qrr Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 10 V, VGS = 4.5 V, ID = 1 A, RGEN = 6 10 14 26 13 20 25 42 23 17 ns ns ns ns nC nC nC VDS = 10 V, VGS = 4.5 V ID = 10 A, 12 2 4 Drain-Source Diode Characteristics and Maximum Ratings Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward VGS = 0 V, IS = 2 A Voltage IF = 10 A, Diode Reverse Recovery Time Diode Reverse Recovery Charge diF/dt = 100 A/s (Note 2) 0.7 20 6 2 1.2 A V nS nC Notes: 1. RJA is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RJC are guaranteed by design while RJA is determined by the user' board design. s (a). RJA = 52 C/W when mounted on a 1in2 pad of 2 oz copper, 1.5" x 1.5" x 0.062" thick PCB (b). RJA = 108 C/W when mounted on a minimum pad of 2 oz copper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0% FDM3300NZ Rev E3 (W) FDM3300NZ Typical Characteristics 40 3.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 4.5V 3.0V 2 1.8 VGS = 2.0V 1.6 1.4 2.5V 1.2 1 0.8 3.0V 3.5V ID, DRAIN CURRENT (A) 30 2.5V 20 2.0V 10 4.5V 0 0 0.5 1 1.5 2 VDS, DRAIN-SOURCE VOLTAGE (V) 0 4 8 12 16 20 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.047 RDS(ON), ON-RESISTANCE (OHM) ID = 5A 1.6 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE ID = 10A VGS = 4.5V 0.042 0.037 0.032 TA = 125oC 1.4 1.2 1 0.027 0.022 0.017 0.012 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) 0.8 TA = 25oC 0.6 -50 -25 0 25 50 75 100 o 125 150 TJ, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation with Temperature. 40 VDS = 5V ID, DRAIN CURRENT (A) 30 125oC 20 TA = -55oC 25oC IS, REVERSE DRAIN CURRENT (A) Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 VGS = 0V 10 1 0.1 0.01 0.001 0.0001 TA = 125oC 25oC -55oC 10 0 0.5 1 1.5 2 2.5 3 VGS, GATE TO SOURCE VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDM3300NZ Rev E3 (W) FDM3300NZ Typical Characteristics 5 VGS, GATE-SOURCE VOLTAGE (V) ID = 10A 4 VDS = 5V CAPACITANCE (pF) 10V 3 15V 1800 1500 1200 900 600 300 Crss 0 0 3 6 9 12 15 0 4 8 12 16 20 Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V) Coss f = 1MHz VGS = 0 V Ciss 2 1 0 Figure 7. Gate Charge Characteristics. 100 RDS(ON) LIMIT ID, DRAIN CURRENT (A) 10 1s 1 VGS = 4.5V SINGLE PULSE RJA = 108oC/W TA = 25oC 0.01 0.1 1 10 100 VDS, DRAIN-SOURCE VOLTAGE (V) 10s DC 1ms 10ms 100ms 100us P(pk), PEAK TRANSIENT POWER (W) 50 Figure 8. Capacitance Characteristics. 40 SINGLE PULSE RJA = 108 C/W TA = 25 C 30 20 0.1 10 0 0.001 0.01 0.1 1 t1, TIME (sec) 10 100 1000 Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 RJA(t) = r(t) * RJA RJA =108 C/W P(pk) t1 t2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE TJ - TA = P * RJA(t) Duty Cycle, D = t1 / t2 0.001 0.0001 0.001 0.01 0.1 t1, TIME (sec) 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDM3300NZ Rev E3 (W) FDM3300NZ PSPICE Electrical Model N-Channel .SUBCKT FDM3300NZ 2 1 3 *NOM TEMP=25 DEG C *FEB 26, 2003 CA 12 8 1E-9 CB 15 14 1.2E-9 CIN 6 8 10.8E-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 23.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LGATE 1 9 3.84E-9 LDRAIN 2 5 1.00E-9 LSOURCE 3 7 4E-9 RLGATE 1 9 38.4 RLDRAIN 2 5 10 RLSOURCE 3 7 40 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 8.3E-3 RGATE 9 20 4.2 RSLC1 5 51 RSLCMOD 1E-6 RSLC2 5 50 1E3 RSOURCE 8 7 RSOURCEMOD 3.9E-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*115),3))} .MODEL DBODYMOD D (IS=2E-12 RS=9.9E-3 N=0.90 TRS1=2.1E-3 TRS2=1.0E-6 CJO=4.5E-10 TT=1E-9 M=0.45 IKF=0.3 XTI=2.0) .MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6) .MODEL DPLCAPMOD D (CJO=45E-11 IS=1E-30 N=10 M=0.4) .MODEL MMEDMOD NMOS (VTO=1.05 KP=8 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2) .MODEL MSTROMOD NMOS (VTO=1.31 KP=82 IS=1E-30 N=10 TOX=1 L=1U W=1U) .MODEL MWEAKMOD NMOS (VTO=0.81 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1) .MODEL RBREAKMOD RES (TC1=0.56E-3 TC2=1.00E-7) .MODEL RDRAINMOD RES (TC1=4.6E-3 TC2=10E-6) .MODEL RSLCMOD RES (TC1=2.5E-3 TC2=8E-6) .MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6) .MODEL RVTHRESMOD RES (TC1=-1.85E-3 TC2=-7E-6) .MODEL RVTEMPMOD RES (TC1=-0.7E-3 TC2=0.50E-6) .MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.0 VOFF=0.6) .MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=0.6 VOFF=-1.0) .ENDS LGATE GATE 1 RLGATE CIN 10 RSLC1 51 ESLC DBREAK 11 + EBREAK MWEAK MMED MSTRO LSOURCE 8 RSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 22 7 RLSOURCE SOURC E 3 17 18 DBODY DPLCAP LDRAIN 5 RLDRAIN DRAIN 2 RSLC2 5 51 ESG + EVTEMP RGATE + 18 9 20 22 6 8 EVTHRES + 19 8 6 Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. FDM3300NZ Rev E3 (W) + - 50 RDRAIN 21 16 FDM3300NZ SPICE Thermal Model .SUBCKT FDM3300NZ_THERM TH TL *Thermal Model Subcircuit *Feb 26, 2003 CTHERM1 TH 8 3 CTHERM2 8 7 5 CTHERM3 7 6 7 CTHERM4 6 5 13.2 CTHERM5 5 4 25.4 7 RTHERM2 RTHERM1 8 CTHERM2 CTHERM1 th JUNCTION CTHERM6 4 3 36.21 CTHERM7 3 2 47.54 CTHERM8 2 TL 208.21 RTHERM4 RTHERM3 6 CTHERM4 5 RTHERM5 4 RTHERM6 3 RTHERM7 2 RTHERM8 CTHERM8 CTHERM7 CTHERM6 CTHERM5 CTHERM3 RTHERM1 TH 8 0.04 RTHERM2 8 7 0.05 RTHERM3 7 6 0.06 RTHERM4 6 5 0.07 RTHERM5 5 4 0.085 RTHERM6 4 3 0.095 RTHERM7 3 2 0.25 RTHERM8 2 TL 0.35 .ENDS tl AMBIENT FDM3300NZ Rev E3 (W) FDM3300NZ Dimensional Outline and Pad Layout FDM3300NZ Rev E3 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx FACT ActiveArray FACT Quiet Series Bottomless FASTa CoolFET FASTr CROSSVOLT FRFET DOME GlobalOptoisolator EcoSPARK GTO E2CMOSTM HiSeC EnSignaTM I2C Across the board. Around the world. The Power Franchise Programmable Active Droop DISCLAIMER ImpliedDisconnect PACMAN POP ISOPLANAR Power247 LittleFET PowerTrencha MicroFET QFET MicroPak QS MICROWIRE QT Optoelectronics MSX Quiet Series MSXPro RapidConfigure OCX RapidConnect OCXPro SILENT SWITCHERa OPTOLOGICa SMART START OPTOPLANAR SPM Stealth SuperSOT-3 SuperSOT-6 SuperSOT-8 SyncFET TinyLogica TruTranslation UHC UltraFETa VCX FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. I2 |
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